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FSBH0270NY_F116 Scheda tecnica(PDF) 4 Page - Fairchild Semiconductor |
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FSBH0270NY_F116 Scheda tecnica(HTML) 4 Page - Fairchild Semiconductor |
4 / 16 page © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1 4 Pin Configuration Figure 4. Pin Configuration and Top Mark Information Pin Definitions Pin # Name Description 1 GND Ground . SenseFET source terminal on primary side and internal controller ground. 2 VDD Power Supply . The internal protection circuit disables PWM output as long as VDD exceeds the OVP trigger point. 3 FB Feedback . The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is determined in response to the signal on this pin and the internal current-sense signal. 4 VIN Line-Voltage Detection . The line-voltage detection is used for brownout protection with hysteresis and constant output power limit over universal AC input range. This pin has additional protections that are pull-HIGH latch and pull-LOW auto recovery, depending on the application. NC No Connection . FSBH0F70A_F116 5 HV Startup . For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors. 6 Drain SenseFET Drain . High-voltage power SenseFET drain connection. 7 Drain SenseFET Drain . High-voltage power SenseFET drain connection. 8 Drain SenseFET Drain . High-voltage power SenseFET drain connection. F – Fairchild Logo Z – Plant Code X – 1-Digit Year Code Y – 1-Digit Week Code TT – 2-Digit Die-Run Code T – Package Type (N:DIP) P – Y: Green Package M – Manufacture Flow Code |
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