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FAN3268 Scheda tecnica(PDF) 6 Page - Fairchild Semiconductor |
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FAN3268 Scheda tecnica(HTML) 6 Page - Fairchild Semiconductor |
6 / 16 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3268 • Rev. 1.0.1 6 Electrical Characteristics (Continued) Unless otherwise noted, VDD=12V and TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. ENABLE VENL Enable Logic Low Threshold EN from 5V to 0V 0.8 1.2 V VENH Enable Logic High Threshold EN from 0V to 5V 1.6 2.0 V VHYS Logic Hysteresis Voltage (9) 0.4 V RPU Enable Pull-up Resistance (9) 100 kΩ OUTPUT ISINK Out Current, Mid-Voltage, Sinking (9) Out at VDD/2, CLOAD=0.1µF, f=1kHz 2.4 A ISOURCE Out Current, Mid-Voltage, Sourcing (9) Out at VDD/2, CLOAD=0.1µF, f=1kHz -1.6 A IPK_SINK Out Current, Peak, Sinking (9) CLOAD=0.1µF, f=1kHz 3 A IPK_SOURCE Out Current, Peak, Sourcing (9) CLOAD=0.1µF, f=1kHz -3 A tRISE Output Rise Time (10) CLOAD=1000pF 12 22 ns tFALL Output Fall Time (10) CLOAD=1000pF 9 17 ns tD1 Propagation Delay (10) 0 - 5VIN, 1V/ns Slew Rate 7 14 25 ns tD2 Propagation Delay (10) 0 - 5VIN, 1V/ns Slew Rate 10 19 34 ns Notes: 8. EN inputs have TTL thresholds; refer to the ENABLE section. 9. Not tested in production. 10. See the Timing Diagrams of Figure 4 and Figure 5. Timing Diagrams Figure 4. Non-Inverting Figure 5. Inverting |
Codice articolo simile - FAN3268_11 |
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Descrizione simile - FAN3268_11 |
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