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FAN100 Scheda tecnica(PDF) 3 Page - Fairchild Semiconductor |
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FAN100 Scheda tecnica(HTML) 3 Page - Fairchild Semiconductor |
3 / 16 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN100 Rev. 1.0.2 3 Marking Information ZXYTT FAN100 TPM Figure 4. Top Mark Pin Configuration Figure 5. Pin Configuration Pin Definitions Pin # Name Description 1 CS Current Sense . This pin connects a current-sense resistor to sense the MOSFET current for peak-current-mode control in CV mode and provides for output-current regulation in CC mode. 2 GND Ground . 3 COMI Constant Current Loop Compensation . this pin connects a capacitor and a resistor between COMI and GND for compensation current loop gain. 4 COMV Constant Voltage Loop Compensation . this pin connects a capacitor and a resistor between COMV and GND for compensation voltage loop gain. 5 VS Voltage Sense . This pin detects the output voltage information and discharge time based on voltage of auxiliary winding. This pin connects two divider resistors and one capacitor. 6 GND Ground . 7 VDD Supply . The power supply pin. IC operating current and MOSFET driving current are supplied using this pin. This pin is connected to an external VDD capacitor of typically 10µF. The threshold voltages for startup and turn-off are 16V and 5V, respectively. The operating current is lower than 5mA. 8 GATE PWM Signal Output . This pin outputs PWM signal and includes the internal totem-pole output driver to drive the external power MOSFET. The clamped gate output voltage is 18V. F - Fairchild logo Z- Plant Code X- 1-Digit Year Code Y- 1-Digit Week Code TT: 2-Digit Die Run Code T: Package Type (M=SOP) P: Z: Pb free, Y: Green Package M: Manufacture Flow Code VS GND VDD GATE COMV COMI GND CS |
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