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FFP08S60S Scheda tecnica(PDF) 7 Page - Fairchild Semiconductor |
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FFP08S60S Scheda tecnica(HTML) 7 Page - Fairchild Semiconductor |
7 / 15 page AN-6982 APPLICATION NOTE © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.0 • 6/8/10 7 [STEP-1] Frequency Setting The switching frequency is determined by the timing resistor and capacitor (RT and CT) as: 1 0.56 ≅ ⋅⋅ SW TT f R C (8) The timing capacitor value determines the maximum duty cycle of PFC gate drive signal as: . 1 1 360 DEAD MAX PFC T SW SW t D Cf t =− = − ⋅ ⋅ (9) It is typical to use a 470pF~1nF capacitor for 50~75kHz switching frequency operation, such that maximum duty cycle of 99~98% is obtained. (Design Example) Since the switching frequency is 65kHz, CT is selected as 1nF to obtain maximum duty cycle as: . 1 360 0.98 MAX PFC T SW DC f =− ⋅ ⋅ = Then, the timing resistor is determined as: 1 27 0.56 == Ω T SW T R k fC [STEP-2] Line Sensing Circuit Design FAN6982 senses the RMS value and instantaneous value of line voltage using the VRMS and IAC pins, respectively, as shown in Figure 14. The RMS value of the line voltage is obtained by an averaging circuit using low-pass filter with two poles. Meanwhile, the instantaneous line voltage information is obtained by sensing the current flowing into the IAC pin through RIAC. RMS IN V V Figure 14. Line-Sensing Circuits RMS sensing circuit should be designed considering the nominal operation range of line voltage and brownout protection trip point as: 3 . 12 3 2 2 RMS RMS UVL LINE BO RMS RMS RMS R VV RR R π − = ⋅ ++ (10) 3 . 12 3 2 RMS RMS UVH LINE MIN RMS RMS RMS R VV RR R − < ++ (11) where VRMS-UVL and VRMS-UVH are the brownout/in thresholds of VRMS. It is typical to set RRMS2 as 10% of RRMS1. The poles of the low-pass filter are given as: 1 12 1 2 P RMS RMS f CR π ≅ ⋅⋅ (12) 2 23 1 2 P RMS RMS f CR π ≅ ⋅⋅ (13) To properly attenuate the twice line frequency ripple in VRMS, it is typical to set the poles around 10~20Hz. The resistor RIAC should be large enough to prevent saturation of the gain modulator as: . 2 159 MAX LINE BO IAC V GA R μ ⋅< (14) where VLINE.BO is the brownout protection line voltage, GMAX is the maximum modulator gain when VRMS is 1.08V (which is typically 9 as can be found in the datasheet), and 159µA is the maximum output current of the gain modulator. (Design Example) The brownout protection thresholds are 1.05V (VRMS-UVL) and 1.9V (VRMS-UVH), respectively. Then, the scaling down factor of the voltage divider is: 3 12 3 . 22 1.05 0.0162 72 22 RMS RMS UVL RMS RMS RMS LINE BO RV RR R V π π − =⋅ ++ =⋅ = The startup of the PFC controller at the minimum line voltage is checked as: .3 12 3 2 85 2 0.0162 1.95 1.9 LINE MIN RMS RMS RMS RMS VR V RR R ⋅ =⋅ ⋅ = > ++ The resistors of the voltage divider network are selected as RRMS1=2MΩ, RRMS2=200kΩ, and RRMS3=36kΩ. To place the poles of the low-pass filter at 15Hz and 22Hz, the capacitors are obtained as: 1 3 12 11 53 2 2 15 200 10 RMS PRMS CnF fR ππ == = ⋅⋅ ⋅ ⋅ × 2 3 23 11 200 2 2 22 36 10 RMS PRMS CnF fR ππ ≅= = ⋅⋅ ⋅ ⋅ × The condition for Resistor RIAC is: . 66 2 272 9 5.8 159 10 159 10 MAX LINE BO IAC V R GM −− ⋅⋅ >⋅ = = Ω ×× Therefore, 6M Ω resistor is selected for RIAC. |
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