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SB320 Scheda tecnica(PDF) 7 Page - Fairchild Semiconductor |
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SB320 Scheda tecnica(HTML) 7 Page - Fairchild Semiconductor |
7 / 10 page AN-8024 APPLICATION NOTE © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.1 • 9/18/09 7 changing the system transfer functions as the load current decreases and/or input voltage increases. One simple and practical way to address this problem is designing the feedback loop for low input voltage and full load condition with enough phase and gain margin. When the converter operates in CCM, the RHP zero is lowest in low input voltage and full load condition. The gain increases only about 6dB as the operating condition is changed from the lowest input voltage to the highest input voltage condition under universal input condition. When the operating mode changes from CCM to DCM, the RHP zero disappears, making the system stable. Therefore, by designing the feedback loop with more than 45 degrees phase margin in low input voltage and full load condition, the stability over all the operating ranges can be guaranteed. Figure 9 is a typical feedback circuit mainly consisting of a shunt regulator and a photo-coupler. R1 and R2 form a voltage divider for output voltage regulation. RF and CF are adjusted for control-loop compensation. The maximum source current of the FB pin is about 1mA. The phototransistor must be capable of sinking this current to pull the FB level down at no load. The value of RD, is determined as: −− ⋅> OOPD KA FB D VV V CTR I R (22) where VOPD is the drop voltage of the photodiode, about 1.2V; VKA is the minimum cathode to anode voltage of KA431 (2.5V); and CTR is the current transfer rate of the opto-coupler. Figure 9. Feedback Circuit The feedback compensation network transfer function of Figure 9 is obtained as: ˆ 1/ ˆ 1/ ZC FB I oPC s v vs s ω ω ω + =− ⋅ + (23) where 1 ω = FB I D F R R RC , 1 1 () ZC F F R RC ω = + , and 1 ω = PC FBFB R C . and RFB is the equivalent feedback bias resistor of FSBH- series (5k Ω); and R1, RD, RF, CF and CFB are shown in Figure 10. (Design Example) Assuming CTR is 100%, 3 33 110 51.2 2.5 1.3 110 1 10 − −− − − ⋅> × −− −− < == Ω × × OOPD KA D OOPD KA D VV V CTR R VV V R k The minimum cathode current for KA431 is 1mA. 3 1.2 110 − < =Ω × OPD BIAS V R k 1k Ω resistor is selected for RBIAS. The voltage divider resistors R1 and R2 for VO sensing are selected as 20k Ω and 20kΩ. [STEP-11] Design Input Voltage Sensing Circuit Figure 10 shows a resistive voltage divider with low-pass filter for line-voltage detection of the VIN pin. The VIN voltage is used for brownout protection, which triggers when the VIN voltage drops below 0.6V. A 500ms debounce time is introduced for brownout protection to prevent false triggering by the voltage ripple on the input capacitor. FSBH-series devices start up when the VIN voltage reaches 1.1V. It is typical to use 100:1 voltage divider for VIN level. Figure 10.Input Voltage Sensing |
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Descrizione simile - SB320 |
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