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LC78631E Scheda tecnica(PDF) 10 Page - Sanyo Semicon Device |
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LC78631E Scheda tecnica(HTML) 10 Page - Sanyo Semicon Device |
10 / 34 page No. 5342-10/34 LC78631E CD D/A Converter Block Diagram 1. HF signal input circuit; Pin 11: EFMI, pin 9: EFMO, pin 79: DEFI, pin 13: CLV+ When an HF signal is input to EFMI, the circuit slices it at an optimal level to produce an EFM (NRZ) signal. To deal with defects, if the DEFI pin (pin 79) goes high, the slice level control output (EFMO, pin 9) goes to the high-impedance state and the slice level is held. However, this function only operates when CLV is in phase control mode, i.e., when the V/P pin (pin 15) is low. This function can be formed by combining with the DEF pin on the LA9230/40 Series LSI. Note: If the EFMI and CLV+ lines are placed too close together, spurious radiation (induced noise) can degrade the error rate. Therefore we recommend laying a ground or VDD shielding line between these lines. 2. PLL clock reproduction circuit; Pin 2: PDO2, pin 3: PDO1, pin 5: FR, pin 7: ISET, pin 21: PCK This block includes a VCO circuit, and a PLL circuit is formed using external resistors and capacitors. ISET is the charge pump reference current, PDO1 and PDO2 are the loop filters, and FR determines the VCO frequency range. (Reference values) R1 = 68 k Ω, C1 = 0.1 µF R2 = 680 Ω, C2 = 0.1 µF R3 = 680 Ω, C3 = 0.047 µF R4 = 1.2 k Ω 3. Synchronization detection monitor; Pin 22: FSEQ This pin outputs a high level when the frame sync (positive synchronizing signal), which is read by PCK from the EFM signal, and the timing (the inserted synchronizing signal), which is generated by a counter, agree. Thus this pin functions as a synchronization monitor. Note that it is held high during one frame. |
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