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LC74793 Scheda tecnica(PDF) 8 Page - Sanyo Semicon Device |
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LC74793 Scheda tecnica(HTML) 8 Page - Sanyo Semicon Device |
8 / 24 page No. 5966-8/24 LC74793, 74793JM Command 0 (Clock Settings Command) • First byte DA 0 to 7 Register Contents Notes Status Function 7 — 1 First byte identification bit 6 — 1 Command 0 identification code. 5 — 1 Clock settings. 4 — 1 3 — 0 2 — 0 1 — 0 0 — 0 • Second byte Setting for the frequency input to the XtalIN pin (pin 2). CDLR can be deleted: The resistor connected to the CDLR pin may be removed. DA 0 to 7 Register Contents Notes Status Function 7 — 0 Second byte identification bit 6 FS 0 1 5 FS2 0 1 4 FS3 0 1 3 — 0 2 TSTMOD 0 Normal operating mode This bit must be set to 0. 1 Test mode 1 — 0 0 SYSRST 0 1 All registers are reset FS FS2 FS3 Setting 0 0 0 2FSC 1 0 0 4FSC (CDLR can be deleted) 0 1 1 FSC 0 0 1 2FSC (CDLR can be deleted) |
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