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LC66P516 Scheda tecnica(PDF) 7 Page - Sanyo Semicon Device |
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LC66P516 Scheda tecnica(HTML) 7 Page - Sanyo Semicon Device |
7 / 26 page Continued from preceding page. Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD. CMOS output: Complementary output. OD output: Open-drain output. User Options 1. Port 0, 1, 4, 5, and 8 output level at reset option The output levels at reset for I/O ports 0, 1, 4, 5, and 8, in independent 4-bit groups, can be selected from the following two options. 2. Oscillator circuit options • Main clock Note: There is no RC oscillator option. • Sub-clock No. 5485-7/26 LC665304A, 665306A, 665308A, 665312A, 665316A Pin I/O Overview Output driver type Options State after a Standby mode reset operation OSC1 OSC2 RES TEST VDD VSS System clock oscillator connections When an external clock is used, leave OSC2 open and connect the clock signal to OSC1. System reset input When the P33/HOLD pin is at the high level, a low level input to the RES pin will initialize the CPU. CPU test pin This pin must be connected to VSS during normal operation. Power supply pins I O I I Ceramic oscillator or external clock selection Selected as an option Hold mode: Oscillator stopped Halt mode: Oscillator operates Option Circuit Conditions and notes 1. External clock 2. Ceramic oscillator The input has Schmitt characteristics Option Circuit Conditions and notes 1. Ports PE0 and PE1 2 Sub-oscillator (crystal oscillator) Option Conditions and notes 1. Output high at reset The four bits of ports 0, 1, 4, 5, or 8 are set in a group 2. Output low at reset The four bits of ports 0, 1, 4, 5, or 8 are set in a group OSC1 OSC1 OSC2 C1 C2 Ceramic oscillator DSB Input data XT1 XT2 C1 C2 Crystal oscillator |
Codice articolo simile - LC66P516 |
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Descrizione simile - LC66P516 |
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