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ADXRS453 Scheda tecnica(PDF) 5 Page - Analog Devices |
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ADXRS453 Scheda tecnica(HTML) 5 Page - Analog Devices |
5 / 32 page ADXRS453 Rev. 0 | Page 5 of 32 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADXRS453 TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SCLK MOSI AVDD DVSS RSVD AVSS RSVD CP5 DVDD RSVD RSVD MISO PDD PSS VX CS Figure 3. Pin Configuration, 16-Lead SOIC_CAV Table 4. Pin Function Descriptions, 16-Lead SOIC_CAV Pin No. Mnemonic Description 1 DVDD Digital Regulated Voltage. See Figure 26 for the application circuit diagram. 2 RSVD Reserved. This pin must be connected to DVSS. 3 RSVD Reserved. This pin must be connected to DVSS. 4 CS Chip Select. 5 MISO Master In/Slave Out. 6 PDD Supply Voltage. 7 PSS Switching Regulator Ground. 8 VX High Voltage Switching Node. See Figure 26 for the application circuit diagram. 9 CP5 High Voltage Supply. See Figure 26 for the application circuit diagram. 10 RSVD Reserved. This pin must be connected to DVSS. 11 AVSS Analog Ground. 12 RSVD Reserved. This pin must be connected to DVSS. 13 DVSS Digital Signal Ground. 14 AVDD Analog Regulated Voltage. See Figure 26 for the application circuit diagram. 15 MOSI Master Out/Slave In. 16 SCLK SPI Clock. |
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