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LC72121 Scheda tecnica(PDF) 9 Page - Sanyo Semicon Device |
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LC72121 Scheda tecnica(HTML) 9 Page - Sanyo Semicon Device |
9 / 22 page No. 5815-9/22 LC72121, 72121M, 72121V DI Control Data No. Control block/data Function Related data 1 Programmable divider data P0 to P15 DVS, SNS • Specifies the divisor for the programmable divider. This is a binary value in which P15 is the MSB. The LSB changes depending on DVS and SNS. (* : don’t care) * LSB: When P4 is the LSB, P0 to P3 are ignored. 2 Reference divider data R0 to R3 XS • Reference frequency selection * PLL INHIBIT mode In this mode, the programmable divider and the IF counter block are stopped, the FMIN, AMIN, and IFIN pins are pulled down to ground, and the charge pump output goes to the high-impedance state. • Crystal oscillator element selection data XS = 0: 4.5 MHz XS = 1: 7.2 MHz Note that 7.2 MHz is selected after a power on reset. 3 IF counter control data CTE GT0, GT1 IFS • IF counter measurement start command data CTE = 1: Starts the counter CTE = 0: Resets the counter • Determines the IF counter measurement time. DVS SNS LSB Set divisor (N) Actual divisor 1 * P0 272 to 65535 Twice the set value 0 1 P0 272 to 65535 The set value 0 0 P4 4 to 4095 The set value GT1 GT0 Measurement time Wait time 0 0 4 ms 3 to 4 ms 0 1 8 3 to 4 1 0 32 7 to 8 1 1 64 7 to 8 R3 R2 R1 R0 Reference frequency 0 0 0 0 100 kHz 0 0 0 1 50 0 0 1 0 25 0 0 1 1 25 0 1 0 0 12.5 0 1 0 1 6.25 0 1 1 0 3.125 0 1 1 1 3.125 1 0 0 0 10 1 0 0 1 9 1 0 1 0 5 1 0 1 1 1 1 1 0 0 3 1 1 0 1 15 1 1 1 0 PLL INHIBIT + Xtal OSC STOP 1 1 1 1 PLL INHIBIT • These pins select the signal input to the programmable divider (FMIN or AMIN) and switch the input frequency range. * See the “Structure of the Programmable Divider” section for details. * See the “Structure of the IF Counter” section for details. DVS SNS Input pin Frequency range accepted by the input pin 1 * FMIN 10 to 160 MHz 0 1 AMIN 2 to 40 MHz 0 0 AMIN 0.5 to 10 MHz (* : don’t care) Continued on next page. |
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