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LC66P5316 Scheda tecnica(PDF) 11 Page - Sanyo Semicon Device |
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LC66P5316 Scheda tecnica(HTML) 11 Page - Sanyo Semicon Device |
11 / 13 page No. 5996-11/13 LC662104A, 662106A, 662108A Parameter Symbol Conditions Ratings min typ max Unit Note P2, P3 (except for the P33/HOLD pin), P4, IIH1 P51, and P53: VIN = 13.5 V, with the output 5.0 µA 1 Input high-level current Nch transistor off IIH2 P0, P1, P50, P52, OSC1, RES, and P33/HOLD: 1.0 µA 1 VIN = VDD, with the output Nch transistor off Input low-level current IIL1 P0, P1, P2, P3, P4, and P5: –1.0 µA 2 VIN = VSS, with the output Nch transistor off Output high-level voltage VOH1 P2, P3 (except for the IOH = –1 mA VDD – 1.0 V 3 P33/HOLD pin) IOH = –0.1 mA VDD – 0.5 Value of the output pull-up resistor RPO P0, P1, P4, P5 30 100 150 k Ω VOL1 P0, P1, P2, P3, P4, and P5 0.4 V 5 Output low-level voltage (except for the P33/HOLD pin): IOL = 1.6 mA VOL2 P0, P1, P2, P3, P4, and P5 1.5 V (except for the P33/HOLD pin): IOL = 8 mA IOFF1 P2, P3, P4, P51, and P53: VIN = 13.5 V 5.0 µA 6 Output off leakage current IOFF2 Does not apply to P2, P3, P4, P51, and P53: 1.0 µA 6 VIN = VDD [Schmitt characteristics] Hysteresis voltage VHYS 0.1 VDD High-level threshold voltage VtH P2, P3, P4, P5, and RES 0.5 VDD 0.8 VDD V Low-level threshold voltage VtL 0.2 VDD 0.5 VDD V [Ceramic oscillator] Oscillator frequency fCF OSC1, OSC2: See Figure 2. 4 MHz 4.0 MHz Oscillator stabilization time fCFS See Figure 3. 4 MHz 10.0 ms [Serial clock] Cycle time Input tCKCY 0.9 µs Output 2.0 Tcyc Low-level and high-level Input tCKL 0.4 µs pulse widths Output tCKH 1.0 Tcyc Rise an fall times Output tCKR, tCKF 0.1 µs [Serial input] Data setup time tICK 0.3 µs Data hold time tCKI 0.3 µs [Serial output] SO0: With the timing of Figure 4 and the test Output delay time tCKO load of Figure 5. Stipulated with respect to the 0.3 µs falling edge ( ↓) of SCK0. [Pulse conditions] INT0: Figure 6, conditions under which the INT0 INT0 high and low-level tIOH, tIOL interrupt can be accepted, conditions under 2 Tcyc which the timer 0 event counter or pulse width measurement input can be accepted High and low-level pulse widths tIIH, tIIL INT1, INT2: Figure 6, conditions under which 2 Tcyc for interrupt inputs other than INT0 the corresponding interrupt can be accepted RES high and low-level tRSH, tRSL RES: Figure 6, conditions under which reset 3 Tcyc pulse widths can be applied. Operating current drain IDD OP VDD: 4-MHz ceramic oscillator 4.5 8.0 mA 8 VDD: 4-MHz external clock 4.5 8.0 mA Halt mode current drain IDDHALT VDD: 4-MHz ceramic oscillator 2.5 5.5 mA VDD: 4-MHz external clock 2.5 5.5 mA Hold mode current drain IDDHOLD VDD: VDD = 1.8 to 5.5 V 0.01 10 µA SI0: With the timing of Figure 4. Stipulated with respect to the rising edge ( ↑) of SCK0. SCK0: With the timing of Figure 4 and the test load of Figure 5. Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified. Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the CMOS output specifications are selected. 2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected. 3. With the output Nch transistor off for CMOS output specification pins. 4. With the output Nch transistor off for pull-up output specification pins. 6. With the output Pch transistor off for open-drain output specification pins. 7. Reset state |
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