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LB1872 Scheda tecnica(PDF) 8 Page - Sanyo Semicon Device |
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LB1872 Scheda tecnica(HTML) 8 Page - Sanyo Semicon Device |
8 / 11 page No. 5625-8/11 LB1872 Continued from preceding page. Pin No. Symbol Pin function Equivalent circuit 20 LD Phase lock detector output This pin goes to the on state when the PLL phase is locked. This is an open collector output. 21 N2 Divisor switch Low: 0 to 1.0 V Middle: 2.0 to 3.0 V High: 4.0 V to VREG This pin goes to the middle level when open. 22 N1 Divisor switch and external clock input Low: 0 to 1.5 V High: 3.5 V to VREG This pin functions as the external clock input pin when N2 is at the middle level. This pin goes to the high level when open. 23 S/S Start/stop control Low: Start High: Stop This pin goes to the high level when open. 24 FGS FG pulse-converted output This pin outputs the post-hysteresis comparator FG signal. This is an open collector output. 25 FGOUT FG amplifier output If noise in the FG signal is a problem, e.g. if discharge noise is detected, insert a capacitor (about 0.01 to 0.1 µF) between this pin and ground. Continued on next page. FG schmitt comparator |
Codice articolo simile - LB1872 |
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Descrizione simile - LB1872 |
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