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ATMEGA128A Scheda tecnica(PDF) 37 Page - ATMEL Corporation |
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ATMEGA128A Scheda tecnica(HTML) 37 Page - ATMEL Corporation |
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37 / 386 page  37 8151G–AVR–07/10 ATmega128A 8. System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Manage- ment and Sleep Modes” on page 46. The clock systems are detailed below. Figure 8-1. Clock Distribution 8.1.1 CPU Clock – clk CPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 8.1.2 I/O Clock – clk I/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.’ The I/O clock is also used by the External Interrupt module, but note that some external inter- rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchro- nously when clk I/O is halted, enabling TWI address reception in all sleep modes. General I/O modules Asynchronous Timer/Counter ADC CPU Core RAM clk I/O clk ASY AVR Clock Control Unit clk CPU Flash and EEPROM clk FLASH clk ADC Source clock Watchdog Timer Watchdog Oscillator Reset Logic Clock Multiplexer Watchdog clock Calibrated RC Oscillator Timer/Counter Oscillator Crystal Oscillator Low-Frequency Crystal Oscillator External RC Oscillator External clock |
Codice articolo simile - ATMEGA128A_1 |
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