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ISL33001IRTZ Scheda tecnica(PDF) 3 Page - Intersil Corporation |
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ISL33001IRTZ Scheda tecnica(HTML) 3 Page - Intersil Corporation |
3 / 19 page 3 FN7560.2 September 30, 2010 ISL33002 (8 LD TDFN) TOP VIEW ISL33002 (8 LD MSOP) TOP VIEW ISL33003 (8 LD TDFN) TOP VIEW ISL33003 (8 LD MSOP) TOP VIEW Pin Descriptions NAME NOTES PIN NUMBER FUNCTION VCC1 8VCC1 power supply, +2.3V to +5.5V. Decouple VCC1 to ground with a high frequency 0.01µF to 0.1µF capacitor. VCC2 ISL33002, ISL33003 1 VCC2 power supply, +2.3V to +5.5V. Decouple VCC2 to ground with a high frequency 0.01µF to 0.1µF capacitor. In level shifting applications, SDA_OUT and SCL_OUT logic thresholds are referenced to VCC2 supply levels. Connect pull-up resistors on these pins to VCC2. GND 4 Device Ground Pin EN ISL33001 1 Buffer Enable Pin. Logic “0” disables the device. Logic “1” enables the device. Logic threshold referenced to VCC1. ISL33003 5 READY ISL33001 only 5 Buffer Active ‘Ready’ Logic Output. When buffer is active, READY is high impedance. When buffer is inactive, READY is low impedance to ground. ACC ISL33002 only 5 Rise Time Accelerator Enable Pin. Logic “0” disables the accelerator. Logic “1” enables the accelerator. Logic threshold referenced to VCC1. SDA_IN 6 Data I/O Pins SDA_OUT 7 SCL_IN 3 Clock I/O Pins SCL_OUT 2 PAD Thermal Pad; TDFN only Thermal pad should be connected to ground or float. Pin Configurations (Continued) 3 2 1 GND 4 6 7 8 5 VCC1 ACC PAD VCC2 SCL_IN SCL_OUT SDA_IN SDA_OUT 6 7 8 5 3 2 1 4 VCC2 GND VCC1 ACC SDA_IN SDA_OUT SCL_IN SCL_OUT 3 2 1 GND 4 6 7 8 5 VCC1 EN PAD VCC2 SCL_IN SCL_OUT SDA_IN SDA_OUT 6 7 8 5 3 2 1 4 VCC2 GND VCC1 EN SCL_IN SCL_OUT SDA_IN SDA_OUT ISL33001, ISL33002, ISL33003 |
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