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SI5338H-A-GM Scheda tecnica(PDF) 8 Page - Silicon Laboratories |
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SI5338H-A-GM Scheda tecnica(HTML) 8 Page - Silicon Laboratories |
8 / 170 page Si5338 8 Rev. 0.6 Input Impedance RIN 10 — — k Input Capacitance CIN —3.5 — pF Input Clock (DC-Coupled Single-Ended Input Clock on Pins IN3/4) Frequency fIN CMOS 5 — 200 MHz Input Voltage VI –0.1 — 3.63 V Input Voltage Swing 200 MHz 0.8 — VDD+10% Vpp Rise/Fall Time tR/tF 20%–80% — — 2 ns Duty Cycle2,3 DC < 4 ns tr/tf 40 — 60 % Input Capacitance CIN —2.0 — pF Output Clocks (Differential) Frequency4 fOUT LVPECL, LVDS 0.16 — 350 MHz 367 — 473.33 MHz 550 — 710 MHz HCSL 0.16 — 250 MHz LVPECL Output Voltage VOC common mode — VDDO–1.45 V — V VSEPP peak-to-peak single- ended swing 0.55 0.8 0.96 VPP LVDS Output Voltage (2.5/3.3 V) VOC common mode 1.125 1.2 1.275 V VSEPP peak-to-peak single- ended swing 0.25 0.35 0.45 VPP LVDS Output Voltage (1.8 V) VOC common mode 0.8 0.875 0.95 V VSEPP peak-to-peak single- ended swing 0.25 0.35 0.45 VPP HCSL Output Voltage VOC common mode 0.35 0.375 0.400 V VSEPP peak-to-peak single- ended swing 0.575 0.725 0.85 VPP Rise/Fall Time tR/tF 20%–80% — — 450 ps Duty Cycle2 DC 45 — 55 % Table 6. Input and Output Clock Characteristics (Continued) (VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Units Notes: 1. For best jitter performance, keep the input slew rate on pins 1,2,5,6 faster than 0.3 V/ns 2. Not in PLL bypass mode. 3. For best jitter performance, keep the input single ended slew rate on pins 3 or 4 faster than 1 V/ns 4. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. 5. Includes effect of internal series 22 resistor. |
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