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KMPC8568VTANGGA Scheda tecnica(PDF) 6 Page - Freescale Semiconductor, Inc |
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KMPC8568VTANGGA Scheda tecnica(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 139 page MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 6 Freescale Semiconductor MPC8568E Overview • TCP/IP acceleration and QoS features: — IP v4 and IP v6 header recognition on receive — IP v4 header checksum verification and generation — TCP and UDP checksum verification and generation — Per-packet configurable acceleration — Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS stacks, and ESP/AH IP-security headers — Supported in all FIFO modes — Transmission from up to eight physical queues — Reception to up to eight physical queues • Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex): — IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or software-programmed PAUSE frame generation and recognition) • IEEE Std 802.1™ virtual local area network (VLAN) tags and priority • VLAN insertion and deletion – Per-frame VLAN control word or default VLAN for each eTSEC – Extracted VLAN control word passed to software separately • Programmable Ethernet preamble insertion and extraction of up to 7 bytes • MAC address recognition • Ability to force allocation of header information and buffer descriptors into L2 cache 1.2.6 DDR SDRAM Controller The MPC8568E supports DDR SDRAM and DDR2 SDRAM. The memory interface controls main memory accesses and provides for a maximum of 16 Gbytes of main memory. The MPC8568E supports a variety of SDRAM configurations. SDRAM banks can be built using DIMMs or directly-attached memory devices. Sixteen multiplexed address signals provide for device densities of 64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1 Gbits, 2 Gbits and 4 Gbits. Four chip select signals support Table 1. Supported eTSEC1 and eTSEC2 Configurations1 1 Both interfaces must use the same voltage (2.5 or 3.3 V). Mode Option eTSEC1 eTSEC2 Ethernet standard interfaces TBI, GMII, or MII TBI, GMII, or MII Ethernet reduced interfaces RTBI, RGMII, or RMII RTBI, RGMII, or RMII FIFO and mixed interfaces 8-bit FIFO TBI, GMII, MII, RTBI, RGMII, RMII, or 8-bit FIFO TBI, GMII, MII, RTBI, RGMII, RMII, or 8-bit FIFO 8-bit FIFO 16-bit FIFO Not used/not available |
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