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CA5420AM Scheda tecnica(PDF) 2 Page - Intersil Corporation |
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CA5420AM Scheda tecnica(HTML) 2 Page - Intersil Corporation |
2 / 8 page 2 FN1925.6 December 8, 2009 Pinout CA5420A (8 LD SOIC) TOP VIEW NOTE: Pin is connected to Case. Ordering Information PART NUMBER (Note 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # CA5420AM 5420A -55 to +125 8 Ld SOIC M8.15 CA5420AMZ (Notes 1, 2) 5420 AMZ -55 to +125 8 Ld SOIC (Tape and Reel) M8.15 NOTES: 1. Add “96” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. 3. For Moisture Sensitivity Level (MSL), please see device information page for CA5420A. For more information on MSL please see techbrief TB363. 1 2 3 4 8 7 6 5 + V+ OFFSET INV. INPUT V- NON-INV. INPUT STROBE OUTPUT OFFSET NULL NULL - CA5420A |
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