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ISL5314INZ Scheda tecnica(PDF) 3 Page - Intersil Corporation |
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ISL5314INZ Scheda tecnica(HTML) 3 Page - Intersil Corporation |
3 / 17 page 3 FN4901.3 January 19, 2010 Typical Application Circuit (Parallel Control Mode, Sinewave Generation) 50 Ω +5V POWER SOURCE 1µF 50 Ω FERRITE 10µH RSET AVP-P AVP-P 0.1µF 0.1µF 0.1µF AVP-P 0.1µF DVP-P 0.1µF + 10µF 1µF FERRITE 10µH BEAD DVP-P + 10µF 0.1µF 0.1µF (IOUTA) ANALOG OUTPUT (DIGITAL POWER PLANE) (ANALOG POWER PLANE) 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 A2 A3 PH0 PH1 SSYNC DVDD SCLK DGND DGND SDATA DVDD DGND C2 C1 C0 ENOFR DGND RESET UPDATE COMPOUT REFLO REFIO CLK DVDD ISL5314 C7:C0 BUS µPROCESSOR/ A3:A0 BUS WRITE ENABLE WRITE CLOCK (WR) DVP-P 0.1µF 0.1µF DVP-P CLOCK FPGA/CPLD SOURCE BEAD 2k Ω SDATA, SSYNC, SCLK (IN PARALLEL CONTROL MODE, SERIAL CONTROL CAN ALSO BE USED IF DESIRED.) 3 4 8 DGND AGND fCLK ISL5314 |
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