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ISL54500 Scheda tecnica(PDF) 8 Page - Intersil Corporation |
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ISL54500 Scheda tecnica(HTML) 8 Page - Intersil Corporation |
8 / 13 page 8 FN6549.2 November 9, 2009 Supply Sequencing And Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 9). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provide additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 9). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Connecting Schottky diodes to the signal pins (as shown in Figure 9) will shunt the fault current to the supply or to ground, thereby protecting the switch. These Schottky diodes must be sized to handle the expected fault current. Power-Supply Considerations The ISL54500 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL54500 5.5V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.8V but the part will operate with a supply below 1.8V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the “Electrical Specifications” tables starting on page 3 and the ”Typical Performance Curves” starting on page 9 for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies because the input switching point becomes negative in this configuration. Logic-Level Thresholds This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2V to 3.6V (see Figure 16). At 3.6V the VIH level is about 0.98V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50Ω systems, the ISL54500 has a -3dB bandwidth of 350MHz (see Figure 17). The frequency response is FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND LATCH-UP IMMUNITY IN COM 100 Ω V+ GND C OPTIONAL PROTECTION RESISTOR NC NO FIGURE 9. OVERVOLTAGE PROTECTION GND VCOM VNX V+ INX OPTIONAL PROTECTION RESISTOR OPTIONAL SCHOTTKY DIODE OPTIONAL SCHOTTKY DIODE ISL54500 |
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