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ISL22449UFV14Z Scheda tecnica(PDF) 2 Page - Intersil Corporation |
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ISL22449UFV14Z Scheda tecnica(HTML) 2 Page - Intersil Corporation |
2 / 13 page 2 FN6333.3 July 17, 2009 Block Diagram SPI INTERFACE VCC GND RW0 RW1 RW2 RW3 SCK SDI SDO CS WR3 WR2 WR1 WR0 SHDN VCC POWER UP INTERFACE, CONTROL AND STATUS LOGIC NON- VOLATILE REGISTERS VCC VCC VCC Pin Descriptions TSSOP PIN SYMBOL DESCRIPTION 1 RW3 “Wiper” terminal of DCP3 2NC 3 SCK SPI clock input 4 SDO SPI open drain data output 5 GND Device ground pin and the RL connection for each DCP 6 RW2 “Wiper” terminal of DCP2 7 RW1 “Wiper” terminal of DCP1 8NC 9CS SPI Chip Select active low input 10 SDI SPI data input 11 NC 12 VCC Power supply pin and the RH connection for each DCP 13 SHDN Shutdown active low input 14 RW0 “Wiper” terminal of DCP0 ISL22449 |
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