5

FN6310.0

July 3, 2006

NOTES:

incremental voltage when changing from one tap to an adjacent tap.

Hysteresis

SDA and SCL Input Buffer Hysteresis

0.05*

V

SDA Output Buffer LOW Voltage,

Sinking 4mA

00.4

V

Cpin

A1, A0, SHDN, SDA, and SCL Pin

Capacitance

10

pF

SCL Frequency

400

kHz

Pulse Width Suppression Time at SDA

and SCL Inputs

Any pulse narrower than the max spec is

suppressed

50

ns

SCL Falling Edge to SDA Output Data

Valid

900

ns

Time the Bus Must be Free before the

Start of a New Transmission

during the following START condition

1300

ns

Clock LOW Time

1300

ns

Clock HIGH Time

600

ns

START Condition Setup Time

SCL rising edge to SDA falling edge; both

600

ns

START Condition Hold Time

600

ns

Input Data Setup Time

window, to SCL rising edge crossing 30% of

100

ns

Input Data Hold Time

window

0ns

STOP Condition Setup Time

600

ns

STOP Condition Hold Time for Read,

or Volatile Only Write

From SDA rising edge to SCL falling edge;

1300

ns

Output Data Hold Time

window

0ns

SDA and SCL Rise Time

20 +

0.1 * Cb

250

ns

SDA and SCL Fall Time

20 +

0.1 * Cb

250

ns

Cb

Capacitive Loading of SDA or SCL

Total on-chip and off-chip

10

400

pF

Rpu

SDA and SCL Bus Pull-up Resistor

Off-chip

For Cb = 400pF, max is about 2~2.5k

Ω

For Cb = 40pF, max is about 15~20k

Ω

1k

Ω

A1 and A0 Setup Time

Before START condition

600

ns

A1 and A0 Hold Time

After STOP condition

600

ns

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

(NOTE 5)

MAX

UNIT

ISL22319