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SI4010 Scheda tecnica(PDF) 7 Page - Silicon Laboratories |
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SI4010 Scheda tecnica(HTML) 7 Page - Silicon Laboratories |
7 / 160 page List of Ta bles Rev. 0.5 7 L IST OF TABLES Table 4.1. Product Selection Guide ......................................................................... 15 Table 6.1. Package Dimensions .............................................................................. 20 Table 6.2. Package Dimensions .............................................................................. 21 Table 7.1. 10-Pin MSOP Dimensions ...................................................................... 23 Table 8.1. PCB Land Pattern Dimensions ............................................................... 25 Table 9.1. Recommended Operating Conditions ..................................................... 26 Table 9.2. Absolute Maximum Ratings1,2 ................................................................ 26 Table 9.3. DC Characteristics .................................................................................. 27 Table 9.4. Si4010 RF Transmitter Characteristics ................................................... 28 Table 9.5. Low Battery Detector Characteristics ...................................................... 31 Table 9.6. Optional Crystal Oscillator Characteristics .............................................. 31 Table 9.7. EEPROM Characteristics ........................................................................ 31 Table 9.8. Low Power Oscillator Characteristics ..................................................... 32 Table 9.9. Sleep Timer Characteristics .................................................................... 32 Table 21.1. CIP-51 Instruction Set Summary .......................................................... 63 Table 23.1. Boot XDATA Status Variables .............................................................. 81 Table 23.2. Run Chip Retest Protection Flags: NVM Programmer .......................... 86 Table 24.1. Special Function Register (SFR) Memory Map .................................... 90 Table 24.2. Special Function Registers ................................................................... 91 Table 24.3. XREG Register Memory Map in External Memory ............................... 94 Table 24.4. XREG Registers .................................................................................... 95 Table 25.1. Interrupt Summary ................................................................................ 98 Table 29.1. 10–Pin Mode ....................................................................................... 113 Table 29.2. 14–Pin Mode ....................................................................................... 113 Table 29.3. GPIO Special Roles ............................................................................ 115 Table 29.4. GPIO Special Roles Control and Order .............................................. 120 |
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