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AD5737 Scheda tecnica(PDF) 10 Page - Analog Devices

Il numero della parte AD5737
Spiegazioni elettronici  Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD5737 Scheda tecnica(HTML) 10 Page - Analog Devices

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AD5757/AD5737
Preliminary Technical Data
Rev. PrD | Page 10 of 31
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 6. 64 LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic
Description
1
RSET_B
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the
IOUT_B temperature drift performance. See the Features section.
2
RSET_A
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the
IOUT_Atemperature drift performance. See the Features section.
3
REFGND
Ground Reference Point for Internal Reference.
4
REFGND
Ground Reference Point for Internal Reference.
5
ADO
Address decode for the DUT on the board.
6
AD1
Address decode for the DUT on the board.
7
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
8
SCLK
Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This operates at clock
speeds of up to 30 MHz.
9
SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
10
SDO
Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 3 and Figure 4.
11
DVDD
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
12
DGND
Digital Ground Pin.
13
LDAC
Load DAC. Active Low Input. This is used to update the DAC registers and consequently the analog
outputs. When tied permanently low the addressed DAC register is updated on the rising edge of SYNC. If
LDAC is held high during the write cycle the DAC input register is updated but the output update only
takes place at the falling edge of LDAC. See Figure 2. Using this mode all analog outputs can be updated
simultaneously. The LDAC pin must not be left unconnected.
14
CLEAR
Active High, Edge Sensitive Input. Asserting this pin sets the Output Current/Voltage to the pre-
programmed CLEAR CODE. Only channels enabled to be cleared will be cleared. See features section for
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SYNC
SCLK
SDIN
SDO
LDAC
FAULT
ALERT
DVDD
DGND
REFGND
AD0
GND_SWB
SWA
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 LFCSP
CLEAR
AVss
AGND
REFGND
AD1
AVCC
RSETA
RSETB
IOUTB
VBOOSTB
SWB
SWC
GND_SWA
SWD
VBOOSTC
IOUTC
COMPDCDC_C
GND_SWC
GND_SWD


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