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ISL54226 Scheda tecnica(PDF) 10 Page - Intersil Corporation |
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ISL54226 Scheda tecnica(HTML) 10 Page - Intersil Corporation |
10 / 18 page ISL54226 10 FN7614.0 July 29, 2010 External VDD Series Resistor to Limit IDD Current during Negative OVP Condition A 100Ω to 1kΩ resistor in series with the VDD pin (see Figure 6) is required to limit the IDD current draw from the system power supply rail during a negative OVP fault event. With a negative -5V fault voltage at both com pins, the graph in Figure 7 shows the IDD current draw for different external resistor values for supply voltages of 2.7V, 3.6V, and 5.25V. Note: With a 500Ω resistor the current draw is limited to around 5mA. When the negative fault voltage is removed the IDD current will return to it’s normal operation current of 25µA to 45µA. The series resistor also provides improved ESD and latch-up immunity. During an overvoltage transient event (such as occurs during system level IEC 61000 ESD testing), substrate currents can be generated in the IC that can trigger parasitic SCR structures to turn ON, creating a low impedance path from the VDD power supply to ground. This will result in a significant amount of current flow in the IC, which can potentially create a latch-up state or permanently damage the IC. The external VDD resistor limits the current during this overstress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. Under normal operation the low microamp IDD current of the IC produces an insignificant voltage drop across the series resistor resulting in no impact to switch operation or performance. CHARGER PORT DETECTION The ISL54226 has special charger port detection circuitry that monitors the voltage at the com pins to detect when a battery charger has been connected into the USB port (see Figure 8). When the battery charger is connected to the USB connector it shorts the COM+ and COM- pins together. The shorting of the pins is sensed by the ISL54226 IC and it pulls the COM+ and COM- lines high and as long as the OE/ALM pin is driven low (OE/ALM = “0”) by the µP, it will drive its INT logic output “Low” to tell the power management circuitry that a battery charger is connected at the port and not a USB host transceiver. The power management circuitry will then set the appropriate current level and use the USB connector VBUS line to charge the battery. FIGURE 6. VDD SERIES RESISTOR TO LIMIT IDD CURRENT DURING NEGATIVE OVP AND FOR ENHANCED ESD AND LATCH-UP IMMUNITY D+ 100Ω TO 1kΩ COM+ COM- VSUPPLY GND C PROTECTION RESISTOR OVP LOGIC D- IDD VDD -5V FAULT VOLTAGE OE/ALM INT LOW TO INDICATE OVP 100kΩ FIGURE 7. NEGATIVE OVP IDD CURRENT vs RESISTOR VALUE vs VSUPPLY FIGURE 8. CHARGER PORT DETECTION 0 5 10 15 20 25 100 200 300 400 500 600 700 800 900 1k RESISTOR (Ω) VCOM+ = VCOM- = -5V 2.7V 3.6V 5.25V D+ COM+ COM- VSUPPLY GND C LOGIC D- VDD OE/ALM INT USB TRANCEIVER BATTERY CHARGER µP 200Ω CHG DET POWER BATTERY CHARGER CIRCUITRY MANAGEMENT “LOW” TO INDICATE CHARGER CONNECTED (OE/ALM = “0”) VBUS GND D+ D- DRIVEN LOW BY µP |
Codice articolo simile - ISL54226_10 |
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Descrizione simile - ISL54226_10 |
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