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KM68257CLP-20 Scheda tecnica(PDF) 8 Page - Samsung semiconductor

Il numero della parte KM68257CLP-20
Spiegazioni elettronici  32Kx8 Bit High Speed Static RAM(5V Operating(, Evolutionary Pin out. Operated at Commercial Temperature Range.
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Produttore elettronici  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM68257CLP-20 Scheda tecnica(HTML) 8 Page - Samsung semiconductor

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KM68257C/CL
CMOS SRAM
PRELIMINARY
Rev 3.0
- 8 -
February-1996
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the ear-
liest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output mus t not
be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
* NOTE : X means Don't Care.
CS
WE
OE
Mode
I/O Pin
Supply Current
H
X
X*
Not Select
High-Z
ISB, ISB1
L
H
H
Output Disable
High-Z
ICC
L
H
L
Read
DOUT
ICC
L
L
X
Write
DIN
ICC
DATA RETENTION CHARACTERISTICS*(TA = 0 to 70
°C)
* L-Ver only.
Parameter
Symbol
Test Condition
Min.
Typ.
Max.
Unit
VCC for Data Retention
VDR
CS
≥VCC - 0.2V
2.0
-
5.5
V
Data Retention Current
IDR
VCC = 3.0V, CS
≥VCC - 0.2V
VIN
≥VCC - 0.2V or VIN≤0.2V
-
-
0.07
§Ì
Data Retention Set-Up Time
tSDR
See Data Retention
Wave form(below)
0
-
-
ns
Recovery Time
tRDR
5
-
-
ms
DATA RETENTION WAVE FORM(CS Controlled)
VCC
4.5V
2.2V
VDR
CS
GND
Data Retention Mode
CS
≥VCC - 0.2V
tSDR
tRDR


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