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KM44V4100C Scheda tecnica(PDF) 1 Page - Samsung semiconductor |
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KM44V4100C Scheda tecnica(HTML) 1 Page - Samsung semiconductor |
1 / 20 page KM44C4000C, KM44C4100C CMOS DRAM KM44V4000C, KM44V4100C This is a family of 4,194,304 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-5 or -6), power consump- tion(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before- RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx4 Fast Page Mode DRAM family is fabricated using Samsung ′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as main memory for high level computer, microcomputer and personal computer. • Part Identification - KM44C4000C/C-L (5V, 4K Ref.) - KM44C4100C/C-L (5V, 2K Ref.) - KM44V4000C/C-L (3.3V, 4K Ref.) - KM44V4100C/C-L (3.3V, 2K Ref.) • Fast Page Mode operation • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Self-refresh capability (L-ver only) • Fast parallel test mode capability • TTL(5V)/LVTTL(3.3V) compatible inputs and outputs • Early Write or output enable controlled write • JEDEC Standard pinout • Available in Plastic SOJ and TSOP(II) packages • Single +5V ±10% power supply (5V product) • Single +3.3V ±0.3V power supply (3.3V product) Control Clocks RAS CAS W Vcc Vss DQ0 to DQ3 A0-A11 (A0 - A10) *1 A0 - A9 (A0 - A10) *1 Memory Array 4,194,304 x 4 Cells SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 4M x 4Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION FEATURES FUNCTIONAL BLOCK DIAGRAM • Refresh Cycles Part NO. VCC Refresh cycle Refresh period Normal L-ver C4000C 5V 4K 64ms 128ms V4000C 3.3V C4100C 5V 2K 32ms V4100C 3.3V • Performance Range Speed tRAC tCAC tRC tPC Remark -5 50ns 13ns 90ns 35ns 5V/3.3V -6 60ns 15ns 110ns 40ns 5V/3.3V • Active Power Dissipation Speed 3.3V 5V 4K 2K 4K 2K -5 324 396 495 605 -6 288 360 440 550 Unit : mW Data out Buffer Data in Buffer OE Note) *1 : 2K Refresh Col. Address Buffer Row Address Buffer Refresh Counter Refresh Control Refresh Timer Column Decoder Row Decoder VBB Generator |
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