KM432S2030C

CMOS SDRAM

REV. 1.1 Mar. '99

- 10

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address

Function

RFU

W.B.L

TM

CAS Latency

BT

Burst Length

BT = 0

Test Mode

Type

Mode Register Set

Reserved

Reserved

Reserved

0

0

1

1

0

1

0

1

Write Burst Length

0

1

Length

Burst

Single Bit

Latency

Reserved

Reserved

2

3

Reserved

Reserved

Reserved

Reserved

CAS Latency

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

Burst Type

0

1

BT = 1

Burst Length

Type

Sequential

Interleave

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

1

2

4

8

Reserved

Reserved

Reserved

Full Page

1

2

4

8

Reserved

Reserved

Reserved

Reserved

POWER UP SEQUENCE

1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

2. RFU (Reserved for future use) should stay "0" during MRS cycle.

Full Page Length : x32 (256)

RFU