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74LVT16501ADL Scheda tecnica(PDF) 6 Page - NXP Semiconductors |
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74LVT16501ADL Scheda tecnica(HTML) 6 Page - NXP Semiconductors |
6 / 19 page 74LVT16501A_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 04 — 19 May 2006 6 of 19 Philips Semiconductors 74LVT16501A 3.3 V LVT 18-bit universal bus transceiver; 3-state 7. Functional description 7.1 Function table [1] H = HIGH voltage level; h = HIGH voltage level one setup time prior to the enable or clock transition; L = LOW voltage level; I = LOW voltage level one setup time prior to the enable or clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state; ↓ = HIGH-to-LOW enable transition; ↑ = LOW-to-HIGH clock transition. VCC 50 voltage supply B2 51 data input or output B2 B1 52 data input or output B1 GND 53 ground (0 V) B0 54 data input or output B0 CPAB 55 A-to-B clock input (active rising edge) GND 56 ground (0 V) Table 3. Pin description …continued Symbol Pin Description Table 4. Function table[1] Operating mode Control Input Internal register Output OEAB LEAB CPAB An Bn OEBA LEBA CPBA Bn An Disabled L H XXXZ Disabled, latch data L ↓ Xh H Z lL Z Disabled, hold data L L H or L X NC Z Disabled, clock data L L ↑ hH Z lL Z Transparent H H X H H H LLL Latch data and display H ↓ Xh H H lL L Clock data and display H L ↑ hH H lL L Hold data and display H L H or L X H H XL L |
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