MC74VHCT86AD datasheet(3/8 Pages) ONSEMI

Il numero della parte	MC74VHCT86AD

Spiegazioni elettronici	Quad 2?묲nput XOR Gate / CMOS Logic Level Shifter with LSTTL?묬ompatible Inputs

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MC74VHCT86A

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DC ELECTRICAL CHARACTERISTICS

VCC

TA = 25°C

TA ≤ 85°C

TA ≤ 125°C

Symbol

Parameter

Test Conditions

(V)

Min

Typ

Max

Min

Max

Min

Max

Unit

VIH

Minimum High−Level

Input Voltage

3.0

4.5

5.5

1.2

2.0

1.2

2.0

1.2

2.0

V

VIL

Maximum Low−Level

Input Voltage

3.0

4.5

5.5

0.53

0.8

0.53

0.8

0.53

0.8

V

VOH

Minimum High−Level

Output Voltage

VIN = VIH or VIL

IOH = −50μA

3.0

4.5

2.9

4.4

3.0

4.5

2.9

4.4

2.9

4.4

V

VIN = VIH or VIL

IOH = −4mA

IOH = −8mA

3.0

4.5

2.58

3.94

2.48

3.80

2.34

3.66

V

VOL

Maximum Low−Level

Output Voltage

VIN = VIH or VIL

IOL = 50μA

3.0

4.5

0.0

0.1

V

VIN = VIH or VIL

IOL = 4mA

IOL = 8mA

3.0

4.5

0.36

0.44

0.52

V

IIN

Maximum Input

Leakage Current

VIN = 5.5V or GND

0 to

5.5

±0.1

±1.0

μA

ICC

Maximum Quiescent

Supply Current

VIN = VCC or GND

5.5

2.0

20

40

μA

ICCT

Quiescent Supply

Current

Input: VIN = 3.4V

5.5

1.35

1.50

1.65

mA

IOPD

Output Leakage

Current

VOUT = 5.5V

0.0

0.5

5.0

10

μA

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

Symbol

Parameter

Test Conditions

TA = 25°C

TA = − 40 to 85°C

Unit

Min

Typ

Max

Min

Max

tPLH,

tPHL

Propagation Delay,

A or B to Y

VCC = 3.3 ± 0.3V

CL = 15pF

CL = 50pF

7.0

9.5

11.0

14.5

1.0

13.0

16.5

ns

VCC = 5.0 ± 0.5V

CL = 15pF

CL = 50pF

4.8

6.3

6.8

8.8

1.0

8.0

10.0

Cin

Input Capacitance

4

10

pF

CPD

Power Dissipation Capacitance (Note 1)

Typical @ 25°C, VCC = 5.0V

pF

18

1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/4 (per gate). CPD is used to determine the

no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.

3.0V

GND

50%

50% VCC

A or B

Y

tPHL

tPLH

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 1. Switching Waveforms

Figure 2. Test Circuit

VOH

VOL

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