CS51312 datasheet(11/22 Pages) ONSEMI

Il numero della parte	CS51312

Spiegazioni elettronici	Synchronous CPU Buck Controller for 12 V Only Applications

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CS51312

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Figure 10. Normal Startup (5.0 ms/div)

Channel 1 − Regulator Input Voltage and VCC1 (10 V/div)

Channel 2 − COMP (2.0 V/div)

Channel 3 − Regulator Output Voltage (1.0 V/div)

Figure 11. Normal Startup Showing Initial Pulse

Followed by Soft Start (5.0 ms/div)

Channel 1 − VCC2 (10 V/div)

Channel 2 − GATE(H) (10 V/div)

Channel 3 − Inductor Switching Node (10 V/div)

Channel 4 − Regulator Output Voltage (2.0 V/div)

If the voltage across the Current Sense resistor generates

a voltage difference between the VFB and VOUT pins that

exceeds the OVC Comparator Offset Voltage (86 mV

typical), the Fault latch is set. This causes the COMP pin to

be quickly discharged, turning off GATE(H) and the upper

NFET since the voltage on the COMP pin is now less than

the 1.1 V PWM comparator offset. The Fault latch is reset

when the voltage on the COMP decreases below the

discharge threshold voltage (0.25 V typical). The COMP

capacitor will again begin to charge, and when it exceeds the

1.1 V PWM comparator offset, the regulator output will Soft

Start normally (see Figure 12).

Figure 12. Startup with COMP Pre−Charged to

2.0 V (2.0 ms/div)

Channel 1 − Regulator Output Voltage (1.0 V/div)

Channel 2 − COMP Pin (1.0 V/div)

Channel 3 − VCC (10 V/div)

When driving large capacitive loads, the COMP must

charge slowly enough to avoid tripping the CS51312

overcurrent protection. The following equation can be used

to ensure unconditional startup:

ICHG

CCOMP

t

ILIM * ILOAD

COUT

where:

ICHG = COMP Source Current (30 μA typical);

CCOMP = COMP Capacitor value (0.1 μF typical);

ILIM = Current Limit Threshold;

ILOAD = Load Current during startup;

COUT = Total Output Capacitance.

Normal Operation

During normal operation, Switch Off−Time is constant

and set by the COFF capacitor. Switch On−Time is adjusted

by the V2 Control loop to maintain regulation. This results

in changes in regulator switching frequency, duty cycle, and

output ripple in response to changes in load and line. Output

voltage ripple will be determined by inductor ripple current

and the ESR of the output capacitors

Transient Response

The CS51312 V2 Control Loop’s 200 ns reaction time

provides unprecedented transient response to changes in

input voltage or output current. Pulse−by−pulse adjustment

of duty cycle is provided to quickly ramp the inductor

current to the required level. Since the inductor current

cannot be changed instantaneously, regulation is maintained

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