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CAT25320LI-T3 Scheda tecnica(PDF) 6 Page - ON Semiconductor

Il numero della parte CAT25320LI-T3
Spiegazioni elettronici  32-Kb SPI Serial CMOS EEPROM
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Produttore elettronici  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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CAT25320LI-T3 Scheda tecnica(HTML) 6 Page - ON Semiconductor

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CAT25320
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6
WRITE OPERATIONS
The CAT25320 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT25320. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
Figure 3. WREN Timing
SCK
SI
SO
00
0
0
0
11
0
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
Figure 4. WRDI Timing
SCK
SI
SO
0
0
000
10
0
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS


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