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CAT24C256WE-GT3 Scheda tecnica(PDF) 3 Page - ON Semiconductor |
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CAT24C256WE-GT3 Scheda tecnica(HTML) 3 Page - ON Semiconductor |
3 / 14 page CAT24C256 http://onsemi.com 3 Table 5. A.C. CHARACTERISTICS (Note 6) (VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Standard VCC = 1.8 V − 5.5 V Fast VCC = 1.8 V − 5.5 V Fast−Plus (Note 9) VCC = 2.5 V − 5.5 V TA = −405C to +855C Units Min Max Min Max Min Max FSCL Clock Frequency 100 400 1,000 kHz tHD:STA START Condition Hold Time 4 0.6 0.25 ms tLOW Low Period of SCL Clock 4.7 1.3 0.55 ms tHIGH High Period of SCL Clock 4 0.6 0.25 ms tSU:STA START Condition Setup Time 4.7 0.6 0.25 ms tHD:DAT Data In Hold Time 0 0 0 ms tSU:DAT Data In Setup Time 250 100 50 ns tR (Note 7) SDA and SCL Rise Time 1,000 300 100 ns tF (Note 7) SDA and SCL Fall Time 300 300 100 ns tSU:STO STOP Condition Setup Time 4 0.6 0.25 ms tBUF Bus Free Time Between STOP and START 4.7 1.3 0.5 ms tAA SCL Low to Data Out Valid 3.5 0.9 0.50 ms tDH Data Out Hold Time 100 100 50 ns Ti (Note 7) Noise Pulse Filtered at SCL and SDA Inputs 100 100 100 ns tSU:WP WP Setup Time 0 0 0 ms tHD:WP WP Hold Time 2.5 2.5 1 ms tWR Write Cycle Time 5 5 5 ms tPU (Notes 7, 8) Power-up to Ready Mode 1 1 0.1 1 ms 6. Test conditions according to “A.C. Test Conditions” table. 7. Tested initially and after a design or process change that affects this parameter. 8. tPU is the delay between the time VCC is stable and the device is ready to accept commands. 9. Fast−Plus (1 MHz) speed class available for product revision “D”, identified by letter “D” marked on top of the package. Table 6. A.C. TEST CONDITIONS Input Levels 0.2 x VCC to 0.8 x VCC Input Rise and Fall Times ≤ 50 ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Levels 0.5 x VCC Output Load Current Source: IL = 3 mA (VCC ≥ 2.5 V); IL = 1 mA (VCC < 2.5 V); CL = 100 pF |
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