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TYN256P Scheda tecnica(PDF) 5 Page - Power Integrations, Inc. |
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TYN256P Scheda tecnica(HTML) 5 Page - Power Integrations, Inc. |
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5 / 20 page  B 8/99 TNY256 5 power level at the lowest input voltage, the calculated inductance will ramp up the current to the current limit before the DC MAX limit is reached. Enable Function TNY256 senses the EN/UV pin to determine whether or not to proceed with the next switch cycle as described earlier. Once a cycle is started, it always completes the cycle (even when the EN/UV pin changes state half way through the cycle). This operation results in a power supply whose output voltage ripple is determined by the output capacitor, amount of energy per switch cycle and the delay of the feedback. The EN/UV pin signal is generated on the secondary by comparing the power supply output voltage with a reference voltage. The EN/UV pin signal is high when the power supply output voltage is less than the reference voltage. In a typical implementation, the EN/UV pin is driven by an optocoupler. The collector of the optocoupler transistor is connected to the EN/UV pin and the emitter is connected to the SOURCE pin. The optocoupler LED is connected in series with a Zener across the DC output voltage to be regulated. When the output voltage exceeds the target regulation voltage level (optocoupler diode voltage drop plus Zener voltage), the optocoupler diode will start to conduct, pulling the EN/UV pin low. The Zener can be replaced by a TL431 device for improved accuracy. The EN/UV pin pull-down current threshold is nominally 50 µA, but is set to 40 µA the instant the threshold is exceeded. This is reset back to 50 µA when the EN/UV pull-down current drops below the current threshold of 40 µA. ON/OFF Control The internal clock of the TNY256 runs all the time. At the beginning of each clock cycle, it samples the EN/UV pin to decide whether or not to implement a switch cycle. If the EN/ UV pin is high (< 40 µA), then a switching cycle takes place. If the EN/UV pin is low (greater than 50 µA) then no switching cycle occurs, and the EN/UV pin status is sampled again at the start of the subsequent clock cycle. At full load, TNY256 will conduct during the majority of its clock cycles (Figure6). At loads less than full load, it will “skip” more cycles in order to maintain voltage regulation at the secondary output. At light load or no load, almost all cycles will be skipped (Figure7). A small percentage of cycles will conduct to support the power consumption of the power supply. The response time of the TNY256 ON/OFF control scheme is very fast compared to normal PWM control. This provides tight regulation and excellent transient response. Power Up/Down The TNY256 requires only a 0.1 µF capacitor on the BYPASS pin. Because of the small size of this capacitor, the power-up delay is kept to an absolute minimum, typically 0.3 ms. Due to the fast nature of the ON/OFF feedback, there is no overshoot at the power supply output. When an external resistor (2 M Ω) is connected to the EN/UV pin, the power MOSFET switching will be delayed during power-up until the DC line voltage exceeds the threshold (100 V). Figures 8 and 9 illustrate the power-up timing waveform of TNY256 in applications with and without an external resistor (2 M Ω) connected to the EN/UV pin. During power-down, when an external resistor is used, the Figure 8. TNY256 Power-up With External Resistor (2 M Ω) Connected to EN/UV Pin. Figure 9. TNY256 Power-up Without External Resistor Connected to EN/UV Pin. 0 12 Time (ms) 0 200 400 5 0 10 0 100 200 V DC-BUS V BYPASS V DRAIN 0 12 Time (ms) 0 200 400 5 0 10 0 100 200 V DC-BUS V BYPASS V DRAIN |
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