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TDA19989AET Scheda tecnica(PDF) 5 Page - NXP Semiconductors |
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TDA19989AET Scheda tecnica(HTML) 5 Page - NXP Semiconductors |
5 / 47 page TDA19989_1 © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 — 15 February 2010 5 of 47 NXP Semiconductors TDA19989 HDMI 1.3 transmitter with HDCP and CEC support 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 3. Pin configuration (TFBGA64) 1 A B C D E F G H ball A1 index area 8 7 6 5 4 3 2 001aal266 TDA19989 Transparent top view Table 2. Pin description Symbol Pin Type[1] Description ACLK H5 I audio clock input AP0 G5 I audio port 0 input AP1 F5 I audio port 1 input HPD E6 I hot plug detect; 5 V tolerant EXT_SWING E7 O TMDS output swing adjustment; place resistor (REXT_SWING =10kΩ± 1 %) between this pin and analog ground. DSDA F6 I/O DDC-bus data input/output; 5 V tolerant DSCL F7 I DDC-bus clock input; 5 V tolerant VCLK D4 I input video pixel clock HSYNC/HREF F4 I input horizontal synchronization or reference input VSYNC/VREF G4 I input vertical synchronization or reference input DE/FREF H4 I data enable or field reference input CSCL B5 I I2C-bus clock input; 1.8 V to 3.3 V tolerant CSDA A5 I/O I2C-bus data input/output; 1.8 V to 3.3 V tolerant INT B6 I/O interrupt HDMI output (open-drain); this pin is used as Dual function pin selectable through I2C-bus. In calibration mode only this pin is used as input for 10 ms ± 1 % calibration pulse. In operation mode this pin is used to warn the external microprocessor that a special event has occurred for HDMI or CEC TX0 − E8 O negative data channel 0 for TMDS output TX0+ D8 O positive data channel 0 for TMDS output TX1 − C8 O negative data channel 1 for TMDS output |
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