Si3452/3

Rev. 1.0

9

VDD = 3.0 to 3.6 V

Description

Symbol

Test Conditions

Min

Typ

Max

Unit

Serial bus clock frequency

0—

400

kHz

SCL high time

600

—

—

ns

SCL low time

1.3

—

—

μs

SCL, SDA rise time

20

—

300

ns

SCL, SDA fall time

20

—

150

ns

Bus free time

Between START and STOP

conditions.

1.3

—

—

μs

Start hold time

Between START and first low SCL.

600

—

—

ns

Start setup time

Between SCL high and START

condition.

600

—

—

ns

Stop setup time

Between SCL high and STOP

condition.

600

—

—

ns

Data hold time

200

—

—

ns

Data setup time

200

—

—

ns

Time from hardware or soft-

traffic

Reset to start condition

—

—

100

ms

Delay from event to INT pin

low or from clear-on-read to

INT pin high

——

5

ms

Notes:

1. Not production tested (guaranteed by design).

3. The Si3452/3 will stretch (pull down on) SCK during the ACK time period if required. The maximum SCL stretching is

SCL

D7

SDA

D6

D5

D4

D3

D0

Start Bit

Stop Bit