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CDCE72010RGCR Scheda tecnica(PDF) 7 Page - Texas Instruments |
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CDCE72010RGCR Scheda tecnica(HTML) 7 Page - Texas Instruments |
7 / 73 page TIMING REQUIREMENTS CDCE72010 www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009 over recommended ranges of supply voltage, load, and operating free-air temperature (1) (2) (3) (4) PARAMETER MIN TYP MAX UNIT PRI_REF/SEC_REFIN fREF - Single For single-ended inputs ( LVCMOS) on PRI_REF and SEC_REF 250 MHz For differential inputs (LVDS and LVPECL) on PRI_REF and fREF - Diff SEC_REF 500 MHz (R divider set to DIV2) Duty Cycle 60% Duty cycle of PRI_REF or SEC_REF at VCC/2 40% Single Duty Cycle Duty cycle of PRI_REF or SEC_REF at VCC/2 40% 60% Diff VCXO_IN, AUX_IN fREF - Single For single-ended inputs ( LVCMOS) 250 MHz fREF - Diff For differential inputs (LVDS and LVPECL) 1500 MHz Duty Cycle 60% Duty cycle of PRI_REF or SEC_REF at VCC/2 40% Single Duty Cycle Duty cycle of PRI_REF or SEC_REF at VCC/2 40% 60% Diff SPI/Control (SPI Bus Timing) fCTRL_CLK CTRL_CLK frequency 20 MHz t2 SPI_MOSI to SPI_CLK setup time 10 ns t3 SPI_MOSI to SPI_CLK hold time 10 ns t4 SPI_CLK high duration 25 ns t5 SPI_CLK low duration 25 ns t1 SPI_LE to SPI_CLK setup time 10 ns t6 SPI_CLK to SPI_LE setup time 10 ns t7 SPI_LE pulse width 20 ns t8 SPI_MISO to SPI_CLK data valid (first valid bit after LE) 10 ns PD, RESET, Hold, REF_SEL Rise and fall time of the PD, RESET, Hold, REF_SEL signal from 20% tr/tf 4 ns to 80% of VCC (1) From 250MHz to 500MHz is achieved by setting the divide by 2 in P’ (2) If the feedback clock (derived from the VCXO input) is less than 2MHz, the device stays in normal operation mode but the frequency detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This affects the HOLD-Over-Function as well as the PLL_LOCK signal is no longer valid. (3) Use a square wave for lower frequencies (< 80 MHz). (4) Slew rate requirement Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): CDCE72010 |
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