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DAC5681IRGCT Scheda tecnica(PDF) 10 Page - Texas Instruments |
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DAC5681IRGCT Scheda tecnica(HTML) 10 Page - Texas Instruments |
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10 / 47 page  DAC5681 SLLS864A – AUGUST 2007 – REVISED JANUARY 2009 ................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS INTERFACE: SDO, SDIO, SCLK, SDENB, RESETB VIH High-level input voltage 2 3 V VIL Low-level input voltage 0 0 0.8 V IIH High-level input current ±20 µA IIL Low-level input current ±20 µA CMOS Input 5 CI pF capacitance IOVDD Iload = –100 µA V –0.2 VOH SDO, SDIO 0.8 Iload = –2mA V x IOVDD Iload = 100 µA 0.2 V VOL SDO, SDIO Iload = 2 mA 0.5 V Setup time, SDENB to ts(SDENB) 20 ns rising edge of SCLK Setup time, SDIO valid ts(SDIO) 10 ns to rising edge of SCLK Hold time, SDIO valid th(SDIO) 5 ns to rising edge of SCLK t(SCLK) Period of SCLK 100 ns t(SCLKH) High time of SCLK 40 ns t(SCLKL) Low time of SCLK 40 ns Data output delay after td(Data) 10 ns falling edge of SCLK Minimum RESETB tRESET 25 ns pulse width CLOCK INPUT (CLKIN/CLKINC) Duty cycle 50% Differential voltage(3) 0.4 1 V CLKIN/CLKINC input CLKVDD V common mode ÷2 (3) Driving the clock input with a differential voltage lower than 1V will result in degraded performance. 10 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5681 |
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