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DAC1403D160HW Scheda tecnica(PDF) 10 Page - NXP Semiconductors |
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DAC1403D160HW Scheda tecnica(HTML) 10 Page - NXP Semiconductors |
10 / 19 page DAC1403D160_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 14 August 2008 10 of 19 NXP Semiconductors DAC1403D160 Dual 14 bits DAC, up to 160 MHz, 2 x interpolating [1] Guaranteed by design. Signal-to-noise ratio S/N signal-to-noise ratio fclk = 80 MHz; BW = Nyquist fo = 2.5 MHz - 80 - dBc fo = 5 MHz 70 80 - dBc fo = 19 MHz - 78 - dBc ACPR adjacent channel power ratio baseband; 5 MHz channel spacing; BW = 3.84 MHz fo = 2.5 MHz - 69 - dBc fo = 20 MHz - 71 - dBc Table 5. Characteristics …continued VCCD =VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = −40 °C to +85 °C; typical values measured at VCCD =VCCA = 3.3 V, IO(fs) = 20 mA and Tamb =25 °C; dynamic parameters measured using output schematic given in Figure 10; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Table 6. Band gap Band gap disable (GAPD) Band gap input/output (GAPOUT) Internal band gap LOW output (VGAPOUT = 1.2 V) enable HIGH input disable Fig 5. Input timing diagram 014aaa511 Q0 to Q13 tsu(i) th(i) CLKN CLK IOUT/IOUTN, QOUT/QOUTN 50 % I0 to I13, |
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