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TPIC8101DW Scheda tecnica(PDF) 6 Page - Texas Instruments |
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TPIC8101DW Scheda tecnica(HTML) 6 Page - Texas Instruments |
6 / 20 page TPIC8101 KNOCK SENSOR INTERFACE SLIS110A − APRIL 2003 − REVISED MAY 2005 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dc electrical characteristics, VDD = 5 V ±5%, input frequency before prescaler = 4 MHz to 20 MHz ( ±0.5%), TA = −40°C to 125°C (unless otherwise specified) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Multiplexer CATTEN Cross-coupling attenuation (assured by design) fin max(ch1) = 20 kHz, measured on channel 2 40 dB Anti-Aliasing Filter fc‡ Cut-off frequency at –3 dB 35 45 55 kHz BW Response 1 kHz to 20 kHz referenced to 1 kHz 70-mV RMS, input: CH1FB or CH2FB, output: OUT −1 −0.5 1 dB ATTEN Attenuation at 100 kHz referenced to 1 kHz 70-mV RMS, input: CH1FB or CH2FB, output: OUT −10 −15 dB Analog-to-Digital Converter fs Sampling frequency For all frequencies stated 198 200 202 kHz AR Analog resolution 10 Bit ADNL Differential linearity error (DNL) 1 Bit AINL Linearity error (INL) 1 Bit Digital-to-Analog Converter fs(DA) Sampling frequency 198 200 202 kHz DR Resolution at 200 kHz 10 Bit DDNL Differential linearity error (DNL) (Vreset < DACout < 0.98 VDD) −1 1 LSB DINL Linearity error (INL) (Vreset < DACout < 0.98 VDD) −2.5 2.5 LSB DRNIL Repeatability (for characterization purposes only) −1 1 LSB Output Buffer VOH High-level output voltage VDD = 5 V, ISource = 2 mA VDD – 0.2 VDD – 0.15 V VOL Low-level output voltage VDD = 5 V, ISink = 2 mA 120 175 mV Av Open-loop gain IO = ±2 mA 60 100 dB G Output gain IO = ±2 mA 1 Vripple Ripple voltage CL = 0 to 22 nF, max slew rate, 12 mV/ µs from Vreset to 4 V 10 mV ts Settling time CL = 0 to 22 nF, max slew rate, 12 mV/ µs from Vreset to 4 V, output: ±0.5 LSB 20 µs ‡ fc is programmable (see Table 1). |
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