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BD00EC0WEFJ-E2 Scheda tecnica(PDF) 10 Page - Rohm |
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BD00EC0WEFJ-E2 Scheda tecnica(HTML) 10 Page - Rohm |
10 / 12 page www.rohm.com 2010.04 - Rev.A © 2010 ROHM Co., Ltd. All rights reserved. BD00GA3WEFJ Technical Note 10/11 (11). Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used. (12). Ground Wiring Pattern. When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. Resistor Transistor (NPN) N N N P + P + P P substrate GND Pin A N N P + P + P P substrate GND Parasitic element Pin B C B E N GND Pin A Pin B Other adjacent elements E B C GND Parasitic element Parasitic element |
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