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CS49325 Scheda tecnica(PDF) 2 Page - Cirrus Logic |
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CS49325 Scheda tecnica(HTML) 2 Page - Cirrus Logic |
2 / 90 page CS49300 Family DSP 2 DS339F7 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ................................................................. 7 1.1 Specified Operating Conditions .................................................................................. 7 1.2 Absolute Maximum Ratings ........................................................................................ 7 1.3 Thermal Data .............................................................................................................. 7 1.4 Digital D.C. Characteristics ......................................................................................... 8 1.5 Power Supply Characteristics ..................................................................................... 8 1.6 Switching Characteristics — RESET ........................................................................ 9 1.7 Switching Characteristics — CLKIN ............................................................................ 9 1.8 Switching Characteristics — Intel® Host Mode ......................................................... 10 1.9 Switching Characteristics — Motorola® Host Mode .................................................. 12 1.10 Switching Characteristics — SPI™ Control Port ..................................................... 14 1.11 Switching Characteristics — I2C® Control Port ....................................................... 16 1.12 Switching Characteristics — Digital Audio Input ..................................................... 18 1.13 Switching Characteristics — Serial Bursty Data Input ............................................. 20 1.14 Switching Characteristics — Parallel Data Input ..................................................... 21 1.15 Switching Characteristics — Digital Audio Output ................................................... 22 2. FAMILY OVERVIEW ....................................................................................................... 24 2.1 CS493XX Document Strategy .................................................................................. 24 2.2 Multichannel Decoder Family of Parts ...................................................................... 24 3. TYPICAL CONNECTION DIAGRAMS ........................................................................... 27 3.1 Multiplexed Pins ........................................................................................................ 27 3.2 Termination Requirements ........................................................................................ 27 3.3 Phase Locked Loop Filter ......................................................................................... 28 4. POWER ........................................................................................................................... 35 4.1 Decoupling ................................................................................................................ 35 4.2 Analog Power Conditioning ....................................................................................... 35 4.3 Ground ...................................................................................................................... 35 4.4 Pads .......................................................................................................................... 35 5. CLOCKING .....................................................................................................................35 6. CONTROL ....................................................................................................................... 36 6.1 Serial Communication ............................................................................................... 36 6.1.1 SPI Communication ...................................................................................... 36 6.1.2 I2C Communication ....................................................................................... 38 6.1.3 INTREQ Behavior: A Special Case .............................................................. 41 6.2 Parallel Host Communication .................................................................................... 44 6.2.1 Intel Parallel Host Communication Mode ...................................................... 46 6.2.2 Motorola Parallel Host Communication Mode .............................................. 47 6.2.3 Procedures for Parallel Host Mode Communication ..................................... 48 7. EXTERNAL MEMORY .................................................................................................... 51 7.1 Non-Paged Memory .................................................................................................. 51 7.2 Paged Memory ......................................................................................................... 52 8. BOOT PROCEDURE & RESET ..................................................................................... 54 8.1 Host Boot ..................................................................................................................54 8.1.1 Serial Download Sequence .......................................................................... 54 8.1.2 Parallel Download Sequence ........................................................................ 57 8.2 Autoboot .................................................................................................................... 57 8.2.1 Autoboot INTREQ Behavior .......................................................................... 60 8.3 Decreasing Autoboot Times Using GFABT Codes (Fast Autoboot) ......................... 61 8.3.1 Design Considerations when using GFABT Codes ...................................... 63 |
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