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74LVT14PW Scheda tecnica(PDF) 6 Page - NXP Semiconductors |
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74LVT14PW Scheda tecnica(HTML) 6 Page - NXP Semiconductors |
6 / 13 page 74LVT14_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 25 April 2008 6 of 13 NXP Semiconductors 74LVT14 3.3 V hex inverter Schmitt trigger Table 8. Measurement points VCC Input Output VM VM 2.7 V to 3.6 V 1.5 V 1.5 V Test data is given in given in Table 9. Definitions for test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 8. Load circuitry for switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aaf615 VCC VI VO DUT CL RT RL PULSE GENERATOR Table 9. Test data Supply Input pulse requirements Load VCC VI Repetition rate tW tr, tf RL CL 2.7 V to 3.3 V 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 500 Ω 50 pF |
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