74LVC_LVCH16374A_7

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Product data sheet

Rev. 07 — 23 March 2010

9 of 19

NXP Semiconductors

74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

10. Dynamic characteristics

[1]

[2]

[3]

Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.

Symbol Parameter

Conditions

−40 °C to +85 °C

−40 °C to +125 °C Unit

Min

Typ[1]

Max

Min

Max

propagation

delay

nCP to nQn; see Figure 7

[2]

-

14

-

-

-

ns

1.5

-

6.0

1.5

7.5

ns

1.5

3.4

5.4

1.5

7.0

ns

enable time

nOE to nQn; see Figure 9

[2]

-

20

-

-

-

ns

1.5

-

6.0

1.5

7.5

ns

1.0

3.5

5.2

1.0

6.5

ns

disable time

nOE to nQn; see Figure 7

[2]

-

12

-

-

-

ns

1.5

-

5.1

1.5

6.5

ns

1.5

3.9

4.9

1.5

6.5

ns

pulse width

nCP HIGH; see Figure 7

-

-

-

-

-

ns

3.0

-

-

3.0

-

ns

3.0

1.5

-

3.0

-

ns

set-up time

nDn to nCP; see Figure 8

-

-

-

-

-

ns

1.9

-

-

1.9

-

ns

1.9

0.3

-

1.9

-

ns

hold time

nDn to nCP; see Figure 8

-

-

-

-

-

ns

1.1

-

-

1.1

-

ns

1.5

−0.3

-

1.5

-

ns

maximum

frequency

see Figure 7

80

-

-

80

-

MHz

100

150

-

100

-

MHz

output skew

time

[3]

-

-

1.0

-

1.5

ns