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74LVC169DB Scheda tecnica(PDF) 11 Page - NXP Semiconductors

Il numero della parte 74LVC169DB
Spiegazioni elettronici  Presettable synchronous 4-bit up/down binary counter
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Produttore elettronici  NXP [NXP Semiconductors]
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74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
11 of 22
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
[1]
Typical values are measured at Tamb =25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2]
tpd is the same as tPLH and tPHL.
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
∑(C
L × VCC
2
× f
o) = sum of outputs
11. Waveforms
fmax
maximum
frequency
see Figure 8
VCC = 2.7 V
150
-
-
150
-
MHz
VCC = 3.0 V to 3.6 V
150
200
-
150
-
MHz
tsk(0)
output skew time
VCC = 3.0 V to 3.6 V
[3]
-
-
1.0
-
1.5
ns
CPD
power dissipation
capacitance
per input pin; VI = GND to VCC
[4]
VCC = 3.0 V to 3.6 V
-
20
-
-
-
pF
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
Measurement points are given in Table 8.
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 8.
Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and the maximum frequency
001aaa651
CP input
Qn, TC output
tPHL
tPLH
tW
1/fmax
VM
VOH
VI
GND
VOL
VM


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