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74HC259PW Scheda tecnica(PDF) 10 Page - NXP Semiconductors |
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74HC259PW Scheda tecnica(HTML) 10 Page - NXP Semiconductors |
10 / 21 page 74HC_HCT259_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 February 2009 10 of 21 NXP Semiconductors 74HC259; 74HCT259 8-bit addressable latch [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. [3] tt is the same as tTHL and tTLH. [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(C L × VCC 2 × f o) = sum of the outputs. 11. Waveforms th hold time D to LE; see Figure 10 and Figure 11 VCC = 4.5 V 0 −8- 0 - 0 - ns An to LE; see Figure 10 and Figure 11 VCC = 4.5 V 0 −4- 0 - 0 - ns CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC − 1.5 V [4] -19 - - - - - pF Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter Conditions 25 °C −40 °Cto+85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Data input to output propagation delays 001aah123 D input Qn output tPHL tPLH GND VCC VM VM VOH VOL |
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