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74HC3G34DP Scheda tecnica(PDF) 7 Page - NXP Semiconductors |
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74HC3G34DP Scheda tecnica(HTML) 7 Page - NXP Semiconductors |
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7 / 13 page  74HC_HCT3G34_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 7 May 2009 7 of 13 NXP Semiconductors 74HC3G34; 74HCT3G34 Triple buffer gate Test data is given in Table 10. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 6. Test circuit for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aad983 DUT VCC VCC VI VO RT RL S1 CL open G Table 10. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH 74HC3G34 GND to VCC ≤ 6 ns 50 pF 1 k Ω open 74HCT3G34 GND to 3 V ≤ 6 ns 50 pF 1 k Ω open |
Codice articolo simile - 74HC3G34DP |
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