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74AUP1G18GM Scheda tecnica(PDF) 3 Page - NXP Semiconductors |
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74AUP1G18GM Scheda tecnica(HTML) 3 Page - NXP Semiconductors |
3 / 19 page 74AUP1G18_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 3 April 2008 3 of 19 NXP Semiconductors 74AUP1G18 Low-power 1-of-2 demultiplexer with 3-state deselected output 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. Fig 2. Pin configuration SOT363 (SC-88) Fig 3. Pin configuration SOT886 (XSON6) Fig 4. Pin configuration SOT891 (XSON6) 74AUP1G18 S1Y GND A2Y 001aae822 1 2 3 6 VCC 5 4 74AUP1G18 GND 001aad869 S A VCC 1Y 2Y Transparent top view 2 3 1 5 4 6 74AUP1G18 GND 001aad870 S A VCC 1Y 2Y Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description S 1 data select GND 2 ground (0 V) A 3 data input 2Y 4 data output VCC 5 supply voltage 1Y 6 data output Table 4. Function table[1] Input Output S A 1Y 2Y LLLZ L HHZ HL Z L HHZ H |
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