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74ABT841PW Scheda tecnica(PDF) 6 Page - NXP Semiconductors |
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74ABT841PW Scheda tecnica(HTML) 6 Page - NXP Semiconductors |
6 / 15 page 74ABT841_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 25 March 2010 6 of 15 NXP Semiconductors 74ABT841 10-bit bus interface latch; 3-state [1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. [2] This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC = 2.1 V to VCC = 5 V ± 10 %, a transition time of up to 100 μs is permitted. [3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. [4] This is the increase in supply current for each input at 3.4 V. 10. Dynamic characteristics ICC supply current VCC = 5.5 V; VI = GND or VCC outputs HIGH-state - 0.5 250 - 250 μA outputs LOW-state - 25 38 - 38 mA outputs disabled - 0.5 250 - 250 μA ΔI CC additional supply current per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND [4] - 0.5 1.5 - 1.5 mA CI input capacitance VI = 0 V or VCC - 4 - - - pF CO output capacitance outputs disabled; VO = 0 V or VCC - 7 - - - pF Table 6. Static characteristics …continued Symbol Parameter Conditions 25 °C −40 °C to +85 °C Unit Min Typ Max Min Max Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 9. Symbol Parameter Conditions 25 °C; V CC = 5.0 V −40 °C to +70 °C; VCC = 5.0 V ± 0.5 V Unit Min Typ Max Min Max tPLH LOW to HIGH propagation delay Dn to Qn; see Figure 5 2.1 4.1 5.5 2.1 6.2 ns LE to Qn; see Figure 6 2.1 4.1 5.9 2.1 6.5 ns tPHL HIGH to LOW propagation delay Dn to Qn; see Figure 5 2.0 4.0 5.5 2.0 6.2 ns LE to Qn; see Figure 6 2.8 4.6 6.2 2.8 6.7 ns tPZH OFF-state to HIGH propagation delay OE to Qn; see Figure 7 1.0 3.0 4.5 1.0 5.3 ns tPZL OFF-state to LOW propagation delay OE to Qn; see Figure 7 2.2 4.1 5.6 2.2 6.3 ns tPHZ HIGH to OFF-state propagation delay OE to Qn; see Figure 7 2.7 4.7 6.2 2.7 7.1 ns tPLZ LOW to OFF-state propagation delay OE to Qn; see Figure 7 2.8 4.6 6.1 2.8 6.5 ns tsu(H) set-up time HIGH Dn to LE; see Figure 8 2.5 1.0 - 2.5 - ns tsu(L) set-up time LOW Dn to LE; see Figure 8 1.5 0 - 1.5 - ns th(H) hold time HIGH Dn to LE; see Figure 8 1.5 0.2 - 1.5 - ns th(L) hold time LOW Dn to LE; see Figure 8 +1.0 −0.8 - 1.0 - ns tWH pulse width HIGH LE; see Figure 6 3.3 1.9 - 3.3 - ns tWL pulse width LOW LE; see Figure 6 3.3 1.9 - 3.3 - ns |
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