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74ABT841PW Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74ABT841PW Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 15 page 74ABT841_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 25 March 2010 2 of 15 NXP Semiconductors 74ABT841 10-bit bus interface latch; 3-state 3. Ordering information 4. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT841D −40 °C to +85 °C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 74ABT841DB −40 °C to +85 °C SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 74ABT841PW −40 °C to +85 °C TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 Fig 1. Logic symbol Fig 2. IEC logic symbol 001aae911 1OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 23 22 21 20 19 18 17 16 23456789 13 LE 15 10 Q8 D8 14 11 Q9 D9 1 1D EN 13 C1 2 23 322 421 520 619 718 817 916 10 15 11 14 001aae912 Fig 3. Logic diagram 001aae913 D LQ D2 LE OE Q2 D LQ D3 Q3 D LQ D4 D LQ D0 Q0 D LQ D1 Q1 Q4 D LQ D5 Q5 D LQ D6 Q6 D LQ D7 Q7 D LQ D8 Q8 D LQ D9 456 23 78910 11 21 20 19 23 13 1 22 18 17 16 15 14 Q9 |
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