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SS8017 Scheda tecnica(PDF) 4 Page - Silicon Standard Corp. |
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SS8017 Scheda tecnica(HTML) 4 Page - Silicon Standard Corp. |
4 / 16 page www.SiliconStandard.com 4 of 16 SS8017 Electrical Characteristics (cont.) Rev.2.01 6/06/2003 SMBus Interface Logic Input High Voltage SMBCLK, SMBDATA; Vcc = 4.5V to 5.5V 2.4 V Logic Input Low Voltage SMBCLK, SMBDATA; Vcc = 4.5V to 5.5V 0.8 V Logic Output Low Sink Current , SMBDATA forced to 0.4V 6 mA Output High Leakage Current forced to 5.5V 1 µA Logic Input Current Logic inputs forced to Vcc or GND -2 2 µA SMBus Input Capacitance SMBCLK, SMBDATA 5 pF SMBus Clock Frequency (Note 4) DC 100 KHz SMBCLK Clock Low Time tLOW , 10% to 10% points 4.7 µs SMBCLK Clock High Time tHIGH , 90% to 90% points 4 µs SMBus Start-Condition Setup Time 4.7 µs SMBus Repeated Start-Condition Setup Time tSU : STA , 90% to 90% points 500 ns SMBus Start-Condition Hold Time tHD: STA , 10% of SMBDATA to 90% of SMBCLK 4 µs SMBus Start-Condition Setup Time tSD: STO , 90% of SMBDATA to 10% of SMBDATA 4 µs SMBus Data Valid to SMBCLK Rising-Edge Time tSU: DAT , 10% or 90% of SMBDATA to 10% of SMBCLK 800 ns SMBus Data-Hold Time tHD : DAT(Note 5) 0 µs SMBCLK Falling Edge to SMBus Data-Valid Time Master clocking in data 1 µs (VCC =full range, TA= 60°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Reset Threshold VTH 4.2 4.4 4.5 V Reset Active Timeout Period 340 ms Output Voltage Low VOL VCC=VTH min ISINK =3.2mA 0.4 V RESET Output Voltage High VOH VCC>VTH max, ISOURCE =5.0mA VCC-1.5 V Note 1: Guaranteed but not 100% tested. Note 2: Quantization error is not included in specifications for temperature accuracy. For example if the SS8017 device temperature is exactly +66.7°C, or +68°C (due to the quantization error plus the +1/2°C offset used for rounding up) and still be within the guaranteed ±3°C error limits for the +60°C to +100°C tem- perature range. See Table3. Note 3: A remote diode is any diode-connected transistor from Table1. TR is the junction temperature of the remote diode. See Remote Diode Selection for remote diode forward voltage requirements. Note 4: The SMBus logic block is a static design that works with clock frequencies down to DC. While slow operation is possible, it violates the 10kHz minimum clock frequency and SMBus specifications, and may monopolize the bus. Note 5: Note that a transition must internally provide at least a hold time in order to bridge the undefined region (300ns max) of SMBCLK's falling edge. (VCC = + 3.3V, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS |
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Descrizione simile - SS8017 |
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